Advanced integrated circuits (ICs) increasingly require more vertical interconnects extending through apertures etched in intervening dielectric layers. The shrinking lateral dimensions of the ICs require that those vertical interconnects have large aspect ratios, that is, the interconnect feature be narrow and deep. These contacts and vias also need to be wired together by horizontally interconnecting wire lines to achieve the required complex electrical paths. The typical fabrication process involves depositing a dielectric layer over a semiconductive or patterned metallic horizontal interconnect layer, photolithographically defining that dielectric layer to have plug holes or other structures extending from its top to its bottom overlying the semiconductive or horizontal interconnect layer, and then depositing a conductive material into the plug holes and possibly above the dielectric layer to simultaneously deposit the material for the horizontal interconnects above that dielectric layer.
The usual integrated circuit, whether it be a memory, logic, or other device, involves a semiconducting silicon substrate into which are formed various regions of different conductivity doping types or doping levels, and these conductivity types and doping levels need to be tightly controlled. As explained previously, one or more dielectric layers are deposited over the silicon, and holes are etched through the respective layers and thereafter filled to form vertical interconnects to the underlying layer, whether it be the silicon or a wiring pattern formed on top of a previously deposited dielectric layer. An upper metal wiring layer is typically deposited simultaneously with the vertical interconnect beneath it. If the vertical interconnect connects at its bottom to silicon, it is referred to as a contact since it contacts silicon, and a proper and stable ohmic contact must be formed between the metal and silicon to avoid undue contact resistance. If the interconnect connects at its bottom to a metal in a multi-level metallization structure, it is referred to as a via. Either a contact or a via can be referred to as a plug or a vertical interconnect, but, unless the interconnect is specified to be otherwise, it will be assumed to be a horizontal interconnect. Vias and contacts are typically circular or nearly square so as to minimize their surface area. However, other holes are sometimes formed in the shape of trenches having one narrow dimension and one long dimension, and these trenches then need to be filled with metal.
A severe problem arises when the hole to be filled has a large aspect ratio. The aspect ratio is the ratio of the depth to the width of a plug formed in a dielectric layer or other type of layer. For a trench, the width that determines the aspect ratio is the smallest lateral dimension. As the density of elements on an integrated circuit has increased, the width of contacts, vias, trenches, and other apertures has decreased while their depth has not substantially decreased because a minimum dielectric thickness is required to electrically isolate stacked layers in the integrated circuit. Hence, the aspect ratio has been increasing. Older technology has generally been limited to filling contacts, vias, and trenches having aspect ratios of 0.5:1 or less. Modern technology uses aspect ratios of up to about 2:1. Advanced technology must adapt to aspect ratios of 5:1 or greater.
If, as is usual, the bulk of the conductive material filled into the plug or trench is a metal, and if further that metal is reactive with the underlying layer or may deleteriously interdiffuse with it, such as occurs with a contact of a metal to silicon, a diffusion barrier layer needs to be coated into the aperture before the metal is deposited therein, and then a thicker bulk metal is filled in over the barrier layer. Titanium nitride (TiN) is presently most commonly used for the barrier layer since it is moderately conductive and, with some added processing, is compatible with both silicon and aluminum.
The hole filling process almost necessarily deposits a metallic layer of laterally varying thickness over the dielectric layer and above the hole. As a result, it is usually necessary to planarize the metallic layer as part of the hole filling process so that subsequent processes can be effected on relatively planar surfaces. A planar surface is particularly required for photolithography, for which an undulatory substrate can defocus the projected pattern. A planar surface is also preferred to underlie thin interconnect lines, which tend to separate in surmounting large vertical steps.
Physical vapor deposition (PVD) is a well known method in the fabrication of integrated circuits both for filling apertures with metals and for depositing planar metal for horizontal interconnects. An example of a modern PVD system is the Endura.RTM. PVD System, available from Applied Materials, Inc. of Santa Clara, Calif. In a standard PVD process, a metal target of the metallic composition desired to be deposited is placed within a plasma reaction chamber in relatively close opposition to the wafer on which the metal is to be deposited. Argon at reduced pressure is filled into the space between the target and the wafer. The metallic target is DC biased sufficiently negatively to the wafer to cause the argon gas to discharge and form an argon plasma. The resultant positive argon ions in the plasma are strongly attracted to the negatively biased target and impact the target at such high energies that atoms or atomic clusters of the target material are dislodged and ejected from the target, that is, sputtered from the target. At least some of the sputtered atoms are deposited on the wafer in a substantially ballistic process. Examples of sputtered metals are aluminum and titanium.
PVD can also be used to sputter deposit compounds such as TiN in a process called reactive sputtering in which the titanium is sputtered from an substantially pure titanium target and reacts with nitrogen gas (or plasma) filling the space intervening between the target and the wafer. The titanium atoms at these relatively low pressures typically undergo a surface reaction with nitrogen after being deposited on the wafer such that the wafer is sputter deposited with TiN. This process is described by Pramanik et al. in "Barrier Metals for ULSI: Deposition and Manufacturing," Solid State Technology, January, 1993, pp. 73-76, 78, 79, 82.
Returning specifically to the sputter deposition of aluminum into plug apertures, FIG. 1 illustrates a substrate 100, here assumed to have a surface portion of either crystalline silicon or polysilicon. The substrate 100 is overlaid with a dielectric layer 102 to form a field oxide or interlayer dielectric. In modern silicon processing, the dielectric layer 102 is usually formed by either thermal growth or plasma-enhanced chemical vapor deposition (PECVD), typically of SiO.sub.2, although other insulators, such as silicate glasses or even organic dielectrics, can be used.
A contact hole 104 is photolithographically defined and then etched through the dielectric layer 102 to extend down to the silicon substrate 100 in order to provide electrical access through the dielectric layer 102 for a patterned upper metal-interconnect level to be formed over the dielectric layer 102 and to contact a specific defined portion of the silicon substrate, such as a source or drain in a MOS transistor. Alternatively, the substrate 100 could be a lower metal-interconnect level, and the hole 104, now called a via hole, is positioned to overlie a metal line formed over the dielectric layer 110 of the lower metal level so as to electrically contact it to another metal line in the upper metal level. Yet further alternatively, a trench aperture can be formed through the dielectric layer 102 and extend a over a relatively large length in the plane out of the illustration but have a relatively narrow width as illustrated, resulting in a high aspect ratio.
FIG. 2 illustrates the result of a standard low-temperature aluminum sputter into a contact hole 104 with a relatively high aspect ratio. A PVD process forms a planar aluminum layer 106 over the level portions of the dielectric layer 102. However, standard PVD produces a substantially isotropic ballistic pattern of aluminum atoms, and in a low-temperature process the sputtered aluminum atoms stick relatively close to where they strike the wafer. As a result, the aluminum layer 106 forms overhangs 108 near the upper corners 110 of the contact hole 104. Once they have formed, the overhangs 108 shield the bottom wall 112 of the contact hole 104 and prevent a substantial direct sputter deposition to fill the hole. The lower portions of the side walls 114 of the contact hole 104 are not favorably oriented for deposition from the isotropic pattern.
If the standard PVD process were continued, as illustrated in the cross section of FIG. 3, the overhangs 108 would coalesce to form a bridge 112 over the contact hole 104, thus creating a void 114 in the deposited aluminum within the contact hole 104. Although the effect is exaggerated in FIG. 3, any included void reduces contact conductivity and introduces a reliability problem. FIG. 3 also shows that a depression 116 tends to form in the sputter deposited aluminum layer 106 over the contact. Even if the formation of voids 114 were avoided, the deposited metal is still insufficiently planar.
For aspect ratios of 1:1 or somewhat higher, the void and planarization problem can be solved by a reflow process. Aluminum tends to migrate or flow at temperatures near or above 480.degree. C., and minimization of surface energy causes the migrating aluminum to fill any non-planar portions, thus completely filling the contact and planarizing the aluminum layer 106, as illustrated in FIG. 4, although a remnant depression 118 likely remains. Reflow can be performed continuously during the sputter deposition by holding the temperature of the substrate 100 at 480.degree. C. or above. Alternatively a high-temperature reflow can be performed after a lower-temperature PVD process.
A typical hole-filling PVD deposition of Al with the cold-hot process to be described later in detail involves initially depositing a seed layer at high power, for a short time, and at a low temperature. The remaining layer is then PVD deposited at lower power, for a longer time, and at a higher temperature. The temperature in the latter step is sometimes referred to as the reflow temperature. It is possible to deposit all the aluminum at a lower temperature and then to reflow the deposited layer at a higher temperature without concurrently depositing further aluminum, but this process takes longer and may introduce discontinuities such as voids in the intermediate structure.
However, reflow is not a complete solution. First, reflow temperatures tend to be somewhat high and to consume a large part of the thermal budget for complex chips. Indeed, the required reflow temperatures may preclude certain low-temperature materials being included in previously formed layers. Advanced dielectrics such a fluorinated silicon oxides or organic polymers, such as polyimide or paralene, require maximum processing temperatures under 400.degree. C. Secondly, reflow fails to avoid voids when the plugs become too narrow, for example, at aspect ratios of 2:1 and above, so that the illustrated geometry is at the edge of the utility of reflow.
Reflow fails to fill plugs with higher aspect ratios because the geometry prevents sufficient material being deposited into the plug hole prior to intense shadowing. The high temperatures of the reflow process also act to aggregate small amounts of the aluminum into hemispherical globules. The globules do not grow to sufficient size to coalesce into a smooth film that uniformly covers the surface before the plug hole is effectively closed off. This problem is partially caused by the fact that aluminum does not readily wet to silicon dioxide. Wetting can be explained in terms of the relative sizes of the surface tension of the free surface of the aluminum and the surface tension between the aluminum and the substrate. Aluminum wets well to Ti, moderately well to TiN, and poorly to SiO.sub.2. Dewetting of aluminum over SiO.sub.2 occurs above 250.degree. C., the exact temperature depending on initial conditions among other parameters. That is, aluminum dewets at a lower temperature than that at which aluminum flows, and the separation of the wetting and flowing regimes prevents easy aluminum reflow unless further steps are taken.
One process intended to overcome this problem in filling narrow plugs problem is called coherent deposition. The particles of metal, e.g., aluminum, sputtered from the target are passed through a collimator with perpendicular apertures having fairly highly aspect ratios. As a result, only those particles traveling nearly perpendicularly to the principal plane of the collimator and hence the principal plane of the substrate freely pass through the collimator. That is, the isotropic ballistic pattern of the sputtered particles is changed to a nearly perpendicular pattern, and the particles can penetrate deeply into the aperture without the formation of shadowing overhangs. But this process is inefficient because the remainder of the particles adhere to the sides of the collimator apertures and the planar matrix portion of the collimator defining the apertures so that much of the sputtered aluminum is lost. A related process, called long throw, widens the separation between the target and the substrate so that the PVD trajectories become more perpendicular. However, since long-throw PVD uses only the nearly perpendicular sputtered particles, its sputtering rate is commensurately reduced.
In a comparative process combining coherent deposition with reflow, an initial coherent (directional) deposition of aluminum is performed at a relatively low temperature of the substrate, for example, 150.degree. C., to form a seed layer within the plug hole. At these temperatures, there is no significant reflow and the atoms stick to the plug bottom 112 (see FIG. 2) where they initially strike. Because of the collimation, the overhang 108 tends to not develop. The geometry for deposition of a collimated beam on the side walls 114 is not favorable, but taking into account backscatter from the plug bottom 112 it is sufficient for a thin, fairly uniform layer to develop.
The collimated, low-temperature PVD is not continued long enough to fill the plug hole because of its uneconomically low deposition rates. Instead, after a stable seed layer has been deposited within the plug hole, the wafer is moved from a coherent PVD chamber to a standard isotropic (i.e., non-coherent) PVD chamber, in which a standard PVD process isotropically deposits aluminum at a high rate and with a substrate temperature ramping up eventually to a temperature sufficient to reflow the deposited aluminum. Because the newly deposited aluminum wets to the already deposited seed layer, the deposited aluminum readily flows as a layer that fills the plug without formation of a void and smooths the exposed layer to be substantially planarized.
It has been observed that very similar results can be obtained in a cold-hot standard, isotropic PVD process that sequentially deposits both the seed layer and the high-temperature, reflowed layer.
As an example of attainable results, if reflow is used to fill aluminum into an aperture with a depth of 1 .2.mu.m and an aspect ratio of about 1:1, a substrate temperature of 480.degree. C. will cause the aluminum to planarize in about three or four minutes. However, reflow has limited effectiveness if the width of the 1.2 .mu.m-deep plug is reduced to 0.5 .mu.m or less, that is, an aspect ratio of 2:1 or higher. Even when plugs are initially deposited by coherent PVD, a standard isotropic deposition process performed at an acceptably low reflow temperature still requires too much time to fill the high-aspect holes.
Although a higher substrate temperature during the high-temperature deposition promotes and accelerates the planarization of aluminum, if the substrate is too hot, the low-temperature seed layer will coalesce into globules and prevent the formation of a conformal film layer. Furthermore, above some substrate temperature for PVD, other previously deposited materials will dimensionally distort or thermally degrade.
Another known method for filling holes with high aspect ratios involves ionizing at least a fraction of the atoms sputtered from the target and then electrically attracting the ionized target atoms to the substrate. The field-controlled movement of the sputtered ions allows the field to be adjusted to cause the sputtered atoms or clusters to be traveling substantially perpendicularly to the plane of the substrate. Thereby, the sputtered material tends to reach to the bottom of the plug holes, as well as the bottom portions of the side walls, and will not collect on the upper edges of the plug holes.
For example, Barnes et al. in U.S. Pat. No. 5,178,739 describe a sputter deposition system which includes a hollow, cylindrical sputter target disposed between an end sputter target and a substrate, all of which are contained within a vacuum chamber. Magnets are disposed on the outside of the vacuum chamber but adjacent to the cylindrical target to increase the argon plasma density adjacent to the target and to thereby increase the amount of material sputtered from the target. RF power is inductively coupled into the chamber between the target and the wafer to create the plasma adjacent to the target. The high level of RF power coupled into the plasma creates a high-density plasma (HDP), which increases the fraction of target atoms that become ionized on their transit to the wafer. The pedestal on which the wafer is supported, and hence the wafer, are DC electrically biased to attract the ionized target atoms. The amount of wafer biasing determines the energy and the directionality of the target atoms as they strike the wafer. Thus, the ionized PVD process is designed so that the ionized target ions, after they pass through the plasma sheath adjacent to the wafer, have a low angular divergence and therefore can uniformly fill the bottoms of apertures, such as plugs, having high aspect ratios. As will be discussed below, other methods are available to create an HDP-PVD process.
Although ionized deposition of a metal is known to be able to fill deep holes, the technique manifests lower deposition rates than standard PVD, thus detracting from the economics of its use, the power requirements are greater, and the equipment is much more expensive than standard PVD equipment. Notwithstanding these disadvantages, many believe that ionized PVD will be required to fill holes with aspect ratios higher than approximately 2:1 and that other techniques, such as coherent PVD followed by standard PVD and reflow, cannot meet the needs of the industry as K line widths continue to shrink.
For contacts in which the aluminum filling the contact hole must electrically contact the underlying silicon, there are additional problems. If the aluminum were allowed to directly physically contact the silicon, the aluminum would diffuse into the silicon and severely disturb its semiconductive properties. Hence, a barrier layer must be formed between the silicon and the contact filling. The typical solution is to deposit a Ti/TiN barrier layer in the contact hole before the aluminum is filled into the plug hole. However, the Ti/TiN barrier layer is typically deposited by PVD, and the resultant TiN is relatively porous so that the aluminum can still diffuse through it. As a result, it has been common practice, as disclosed by Ngan et al. in U.S. Pat. No. 5,378,660, to anneal the PVD-deposited Ti/TiN layer at 450.degree. to 480.degree. C. or possibly somewhat above in an oxygen-containing environment. This treatment "stuffs" oxygen into the TiN pores so as to block any aluminum diffusion.
Normally, a layer of Ti or of a Ti compound such as TiN wets aluminum so that the aluminum tends not to bead on it and more readily flows over it. It is seen that wetting promotes the filling of narrow plug holes at moderate temperatures. However, oxygen stuffing of PVD-deposited TiN severely degrades its wetting properties. To circumvent this effect, Ong has suggested in U.S. Pat. No. 5,371,042 that another, wetting layer of Ti or a Ti-containing material be deposited over the oxygen-annealed TiN barrier layer. This process is more completely illustrated in the flow diagram of FIG. 5. In step 120, a standard PVD process is used to first deposit a Ti layer and to then deposit a TiN layer thereover. In step 122, the wafer is typically moved to a separate annealing chamber to be annealed in an oxygen environment. In step 124, the wafer is moved back to a PVD chamber for the sputter deposition of a Ti layer. In step 126, the wafer is moved to another PVD chamber for the sputter deposition of the aluminum layer in a first cold step followed by a hot, reflow step.
The Ong process seems to provide adequate hole filling for presently contemplated plugs and contacts. However, the process is overly complex, requiring at least two PVD depositions of Ti or TN separated by an anneal in oxygen. It is greatly desired to provide a simpler process for filling plugs of high aspect ratios.
For many applications such as vertical interconnects, the aluminum deposited to fill the contact or via is simultaneously deposited over the planar surface of the dielectric layer 102. Following the deposition of an unillustrated anti-reflection coating usually of TiN, this thin aluminum layer is thereafter photolithographically patterned, as illustrated in the orthographic view of FIG. 6, to form interconnect lines linking different elements by a predetermined wiring pattern, such as the illustrated interconnect 130 connecting two underlying contacts or vias 132, 134 although one or both of the vias 132, 134 may connect to the overlying layer.
For advanced integrated circuits, the wiring pattern can be very dense. Accordingly, the interconnect lines are made relatively narrow. However, the narrowness causes the required levels of current flowing through the interconnects between the electrical elements to produce relatively high current densities in the interconnects. It is a well known problem that high current densities in aluminum causes electromigration of the aluminum away from hot spots, such as caused by a localized small defect 136. But, the migration removes material from the hot spot 136, which reduces the cross section of the interconnect at that point and promotes yet further electromigration. As illustrated orthographically in FIG. 7, the electromigration may cause the hot spot around the small defect 136 to develop into a break 138 in the interconnect 130, thus destroying the electrical connection between the two plugs 132, 134. Thus, electromigration introduces a failure mechanism in which aluminum interconnects become disconnected after a period of use.
It is well known that when the aluminum is deposited on some types of crystallographically oriented TiN, electromigration is reduced. Kim et al. presents such results in "The effect of reactive-sputtered TiN on electromigration of Al alloy metallization", Proceedings IEEE VMIC Conference, Jun. 27-29, 1995 (104/95/0443), p. 443. Campbell et al. present a thorough investigation of the effect in "Relationship Between Texture and Electromigration Lifetime in Sputtered Al-1% Si Thin Films, Journal of Electronic Materials, vol. 22, 1993, pp. 589-596. Knorr et al. relate electromigration to crystallographic orientation of the deposited aluminum film in "The role of texture in the electromigration behavior in pure aluminum films," Journal of Applied Physics, vol. 79, 1996, pp. 2409-2417. It is noted that Knorr et al. report an ion content of 1 to 2% in one method of depositing aluminum. Kordic et al. describe a similar dependence upon crystallographic orientation for another failure mode in "Correlation between stress voiding of Al(Si)(Cu) metallizations and crystal orientation of aluminum grains," Journal of Applied Physics, vol. 74, 1993, pp. 5391-5394. In any case, it is greatly desired that whatever plug-filling process is developed be integratable with a planar process providing satisfactorily low electromigration in interconnects.